Atmel Pro Chip Designer Series CPLDs With

The combination of these tools enables CPLD designers to achieve the highest possible logic utilization from the Atmel ATF15xxASASLASVASVLBE (1) series CPLDs with Logic Doubling features.

Through all of the software components available within ProChip, the following features are supported: Design Entry and Synthesis VHDL Verilog CUPL (2) Schematic (2) Simulation VHDL Functional and Timing Simulation (3) Verilog Functional and Timing Simulation (3) CUPL Functional Simulation (2) Device ATF15xxBE: (1) 1.8V ultra-low-power CPLD ATF15xxASASL: 5.0V standard and low-power CPLD ATF15xxASVASVL: 3.0V standard and low-power CPLD Programming JTAG ISP 1.

The ATF15xxBE is not recommended for new design.

Optional and requires Altium software.

Optional and requires a separate license from Mentor Graphics.

ModelSim ( Optional ) (Atmel-OEM version) VHDL and Verilog simulation supports from Mentor Graphics.

HDL Planner VHDL and Verilog design entry and text editing supports from Atmel.

Optional Third-party Software Protel Design Explorer 99SE (Atmel Edition) Schematic and CUPL design entries, synthesis, and functional simulation supports from Altium.

Atmel Pro Chip Designer Code Are Described

ProChip Designer Software Suite Components and Licensing Terms The software components within ProChip Designer are divided into two groups: SchematicCUPL Design Flow VHDLVerilog Design Flow These two software groups, their contents, licensing terms, and ordering code are described in Table 1-1 below.

Table 1-1. ProChip Designer Contents and Licensing Terms Note: 1.

The Atmel software tools are supported on Microsoft Windows 7810 operating systems.

The details of the operating system supports for other vendors tools can be obtained from the third-party tool vendors websites or documentation.

Default Installation of Software Components By default, the installation of ProChip Designer includes the installation of the following software components: HDL Planner ATF15xx Fitters ATMISP Precision RTL Synthesis ModelSim Design Flow Software Components Licensing Term SchematicCUPL Design Flow ProChip Designer with HDL Planner, Atmel Fitter, and ATMISP.

Permanent License PN: ATDS1500PC VHDLVerilog Design Flow ProChip Designer with HDL Planner, Atmel Fitter, and ATMISP.

Atmel Pro Chip Designer Free Mentor Graphics

Free Mentor Graphics Precision RTL Synthesis (Atmel-OEM version).

License PN: ATDS15xxKSW1 Mentor Graphics ModelSim (Atmel-OEM version).

Contact Mentor Graphics Unlike ProChip Designer v4.0, the installation of Altium tools are no longer included in ProChip Designer v5.0.1 installer.

Optionally, Protel Design Explorer 99SE can be installed separately, and it can be used independently or in conjunction with ProChip Designer v5.0.1 for schematic and CUPL designs.

The Atmel Licensed Edition of Altium Protel Design Explorer 99SE can be ordered from an Atmel distributor and the Atmel.

Table 1-3. Altium Protel Design Explorer 99SE License Once a license has been purchased, instructions on how to obtain ProChip Designer and Protel Design Explorer 99SE along with a 16-digit Access Code (permanent license) will be mailed.

Users can then follow the instructions provided to install the Licensed Edition software.

Please contact Mentor Graphics for information on how to obtain the appropriate license for ModelSim if VHDLVerilog simulation is required.

Permanent License Atmel Ordering Code Altium Protel Design Explorer 99SE ATDS1500PC.

Design Flow The ProChip Designer IDE is shown in Figure 2-1.

The Design Flow chart on the right provides push-button access to all stages of a design cycle.

Feature descriptions for each design flow stage is described in Table 2-1.

Figure 2-1. ProChip Designer IDE Table 2-1.

Description of Design Flow Stages Design Flow Stage Description Source Manager To specify new or existing design file(s).

Launches the appropriate design entry tool for editing based on the selected tool-flow.

Logic Synthesis To synthesize the design file(s) to generate the appropriate netlist file.

Device Fitter To fit the netlist into the target device with the user selected fitter options.

Testbench Manager To specify new or existing testbench file(s).